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publication number S29NS-J_01 revision a amendment 10 issue date march 22, 2006 S29NS-J 128 megabit (8 m x 16-bit), 64 megabit (4 m x 16-bit), 32 megabit (2 m x 16-bit), a nd 16 megabit (1 m x 16 bit), 110 nm cmos 1.8-volt only simultaneous read/write, burst mode flash memories data sheet notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient pr oduction volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.
ii S29NS-J S29NS-J_01_a10 march 22, 2006 data sheet notice on data sheet designations spansion llc issues data sheets with advance in formation or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, in - cluding development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. the following descriptions of spansion data sheet designations are presented here to high - light their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe - cific products, but has not committed any design to production. information presented in a doc - ument with this designation is likely to change , and in some cases, development on the product may discontinue. spansion llc therefore places the following conditions upon advance informa - tion content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the prod - uct life cycle, including product qualification, in itial production, and the su bsequent phases in the manufacturing process that occur before full production is achi eved. changes to the technical specifications presented in a preliminary docume nt should be expected while keeping these as - pects of production under consid eration. spansion places the fo llowing conditions upon prelimi - nary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of pr oducts with different designations (advance in - formation, preliminary, or full pr oduction). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with dc charac teristics table and ac erase an d program table (in the table notes). the disclaimer on the first page refe rs the reader to the notice on this page. full production (no desi gnation on document) when a product has been in produc tion for a period of time such th at no changes or only nominal changes are expected, the preliminary designatio n is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a descript ion or to correct a typographical error or incor - rect specification. spansion llc applies the follo wing conditions to documents in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
march 22, 2006 S29NS-J_01_a10 S29NS-J iii data sheet ta b l e o f c o n t e n t s notice on data sheet designations . . . . . . . . . . . ii advance information ....................................................................................... ii preliminary .......................................................................................................... ii combination ....................................................................................................... ii full production (no designation on document) ................................... ii simultaneous read/write operations with zero latency ......................2 product selector guide . . . . . . . . . . . . . . . . . . . . . .4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram of simultaneous operation circuit 5 connection diagram . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . 12 valid combinations .............................................................................................13 device bus operations . . . . . . . . . . . . . . . . . . . . . 14 table 1. device bus operations ........................................... 14 requirements for asynchronous read operation (non-burst) .......... 14 requirements for synchronous (burst) read operation ....................... 14 continuous burst .............................................................................................15 8-, 16-, and 32-word linear burst with wrap around .......................15 table 2. burst address groups ............................................ 16 8-, 16-, and 32-word linear burst without wrap around ................ 16 programmable wait state ................................................................................ 16 handshaking feature ......................................................................................17 simultaneous read/write operations with zero latency .....................17 writing commands/command sequences ..................................................17 accelerated program operation ................................................................17 autoselect functions ......................................................................................17 standby mode ........................................................................................................17 automatic sleep mode ...................................................................................... 18 reset#: hardware reset input ..................................................................... 18 v cc power-up and power-down sequencing ........................................ 18 output disable mode ........................................................................................ 18 hardware data protection .............................................................................. 18 wp# boot sector protection ......................................................................... 19 low vcc write inhibit ................................................................................ 19 write pulse ?glitch? protection ................................................................ 19 logical inhibit ................................................................................................... 19 common flash memory interface (cfi) . . . . . . 20 table 3. cfi query identification string ................................ 20 table 4. system interface string ......................................... 20 table 5. device geometry definition .................................... 21 table 6. primary vendor-specific extended query ................. 21 table 7. sector address table, s29ns128j ........................... 23 table 8. sector address table, s29ns064j ........................... 27 table 9. sector address table, s29ns032j ........................... 31 table 10. sector address table, s29ns016j ......................... 32 command definitions ........................................................................................33 reading array data ............................................................................................33 set configuration register command sequence ......................................34 table 11. burst modes ....................................................... 34 handshaking feature .....................................................................................34 table 12. wait states for handshaking ................................. 35 sector lock/unlock command sequence ...................................................35 reset command ..................................................................................................35 autoselect command sequence ....................................................................36 table 13. autoselect device id ............................................ 36 program command sequence ........................................................................36 unlock bypass command sequence .........................................................37 figure 1. program operation ............................................... 38 chip erase command sequence ................................................................... 38 sector erase command sequence ................................................................ 39 accelerated sector group erase .............................................................. 39 table 14. accelerated sector erase groups, s29ns128j ......... 40 table 15. accelerated sector erase groups, s29ns064j ......... 40 table 16. accelerated sector erase groups, s29ns032j ......... 41 table 17. accelerated sector erase groups, s29ns016j ......... 41 erase suspend/erase resume commands .................................................. 42 figure 2. erase operation ................................................... 43 table 18. command definitions .......................................... 44 dq7: data# polling ............................................................................................ 45 figure 3. data# polling algorithm ........................................ 46 rdy: ready ...........................................................................................................47 dq6: toggle bit i ............................................................................................... 47 dq2: toggle bit ii .............................................................................................. 47 figure 4. toggle bit algorithm ............................................. 48 table 19. dq6 and dq2 indications ..................................... 49 reading toggle bits dq6/dq2 ..................................................................... 49 dq5: exceeded timing limits ........................................................................ 49 dq3: sector erase timer ................................................................................ 50 table 20. write operation status ......................................... 50 figure 5. maximum negative overshoot waveform ................ 51 figure 6. maximum positive overshoot waveform .................. 51 operating ranges ................................................................................................ 51 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 7. test setup .......................................................... 53 table 21. test specifications ............................................... 53 key to switching waveforms . . . . . . . . . . . . . . . 53 switching waveforms . . . . . . . . . . . . . . . . . . . . . 53 figure 8. input waveforms and measurement levels.............. 53 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 v cc power-up ..................................................................................................... 54 figure 9. v cc power-up diagram.......................................... 54 clk characterization ....................................................................................... 55 figure 10. clk characterization........................................... 55 synchronous/burst read .................................................................................. 56 figure 11. burst mode read (66 and 54 mhz)........................ 56 figure 12. burst mode read (40 mhz) .................................. 57 asynchronous read ........................................................................................... 58 figure 13. asynchronous mode read .................................... 58 figure 14. reset timings .................................................... 59 erase/program operations ..............................................................................60 figure 15. program operation timings ................................. 61 figure 16. chip/sector erase operations............................... 62 figure 17. accelerated unlock bypass programming timing..... 63 figure 18. data# polling timings (during embedded algorithm) ... 64 figure 19. toggle bit timings (during embedded algorithm) ... 64 figure 20. 8-, 16-, and 32-word li near burst address wrap around 65 figure 21. latency with boundary crossing ........................... 65 figure 22. initial access at 3eh with address boundary latency 66 figure 23. example of extended va lid address reducing wait state usage .............................................................................. 66 figure 24. back-to-back read/write cycle timings ................ 67 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . 68 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 69 s29ns128j .............................................................................................................. 69 vdc048?48-ball very thin fine-pitch ball grid array (fbga) 10 x
iv S29NS-J S29NS-J_01_a10 march 22, 2006 data sheet 11 mm package ................................................................................................ 69 s29ns064j ............................................................................................................ 70 vdd044?44-ball very thin fine-pit ch ball grid ar ray (fbga) 9.2 x 8 mm package ................................................................................................. 70 s29ns032j and s29ns016j .................................................................................71 vde044?44-ball very thin fine-pitch ball grid array (fbga) 7.7 x 6.2 mm package ................................................................................................71 table 22. daisy chain part for 128mbit 110 nm flash products (vdc048, 10 x 11 mm) ...................................................... 72 table 23. vdc048 package information ................................ 72 table 24. vdc048 connections ........................................... 72 figure 25. vdc048 daisy chain layout (top view, balls facing down) ............................................. 73 appendix b: daisy chain information . . . . . . . . .74 table 25. daisy chain part for 64mbit 110 nm flash products (vdd044, 9.2 x 8 mm) ....................................................... 74 table 26. vdd044 package information ................................ 74 table 27. vdd044 connections ............................................ 74 figure 26. vdd044 daisy chain layout (top view, balls facing down) ............................................ 75 appendix c: daisy chain information . . . . . . . . . 76 table 28. daisy chain part for 32 and 16 mbit 110 nm flash prod- ucts (vde044, 7.7 x 6.2 mm) .............................................. 76 table 29. vde044 package information ................................ 76 table 30. vde044 connections ............................................ 76 figure 27. vde044 daisy chain layout (top view, balls facing down) ............................................ 77 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . 78
publication number S29NS-J_00 revision a amendment 10 issue date march 22, 2006 distinctive characteristics ? single 1.8 volt read, program and erase (1.7 to 1.95 v) ? multiplexed data and address for reduced i/o count ? a15?a0 multiplexed as dq15?dq0 ? addresses are latched by avd# control input when ce# low ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations ? read access times at 66/54 mhz (c l =30 pf) ? burst access times of 11/13.5 ns at industrial temperature range ? asynchronous random access times of 65/70 ns ? synchronous random access times of 71/87.5 ns ? burst modes ? continuous linear burst ? 8/16/32 word linear bu rst with wrap around ? 8/16/32 word linear burst without wrap around ? power dissipation (typical values, 8 bits switching, c l = 30 pf) ? burst mode read: 25 ma ? simultaneous operation: 40 ma ? program/erase: 15 ma ? standby mode: 9 a ? sector architecture ? four 8 kword sectors ? two hundred fifty-five (s29ns128j), one hundred twenty-seven (s29ns064j),sixty-three (s29ns032j), or thirty-one (s29ns016j) 32 kword sectors ? four banks (see next page for sector count and size) ? sector protection ? software command sector locking ? wp# protects the two highest sectors ? all sectors locked when a cc = v il ? handshaking feature ? provides host system with minimum possible latency by monitoring rdy ? supports common flash memory interface (cfi) ? software command set compatible with jedec 42.4 standards ? backwards compatible with am29f and am29lv families ? manufactured on 110 nm process technology ? embedded algorithms ? embedded erase algorithm automatically preprograms and erases th e entire chip or any combination of designated sectors ? embedded program algorith m automatically writes and verifies data at specified addresses ? data# polling and toggle bits ? provides a software method of detecting program and erase operation completion ? erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? hardware reset input (reset#) ? hardware method to rese t the device for reading array data ? cmos compatible inputs and outputs ? package ? 48-ball very thin fbga (s29ns128j) ? 44-ball very thin fbga (s29ns064j, s29ns032j, s29ns016j) ? cycling endurance: 1 million cycles per sector typical ? data retention: 20 years typical S29NS-J 128 megabit (8 m x 16-bit), 64 megabit (4 m x 16-bit), 32 megabit (2 m x 16-bit), a nd 16 megabit (1 m x 16 bit), 110 nm cmos 1.8 volt-only simultaneous read/write, burst mode flash memories data sheet
2S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet general description the s29ns128j, s29ns064j, s29ns032j and s29ns016j are 128 mbit, 64 mbit, 32 mbit and 16 mbit 1.8 volt-only, simultaneous read/write, bu rst mode flash memory devices, organized as 8,388,608, 4,194,304, 2,097,152 and 1,048,576. words of 16 bits each. these devices use a sin - gle v cc of 1.7 to 1.95 v to read, program, and erase the memory array. a 12.0-volt a cc may be used for faster program performa nce if desired. these devices can also be programmed in stan - dard eprom programmers. the devices are offered at the following speeds: the devices operate within the temperature range of ?25 c to +85 c, and are offered very thin fbga packages. simultaneous read/write oper ations with zero latency the simultaneous read/write architecture divides the memory space into four banks. the device allows a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the devices are structured as shown in the following tables: clock speed burst access (ns) synch. initial access (ns) asynchronous initial access (ns) output loading 66 mhz 11 71 65 30 pf 54 mhz 13.5 87.5 70 s29ns128j bank a sectors bank b, c & d sectors quantity size quantity size 4 8 kwords 64 32 kwords 63 32 kwords 32 mbits total 96 mbits total s29ns064j bank a sectors bank b, c & d sectors quantity size quantity size 4 8 kwords 32 32 kwords 31 32 kwords 16 mbits total 48 mbits total
march 22, 2006 S29NS-J_00_a10 S29NS-J 3 data sheet the devices use chip enable (ce#), write enab le (we#), address valid (avd#) and output en - able (oe#) to control asynchronous read and write operations. for burst operations, the devices additionally require ready (rdy) and clock (clk). this implementation allows easy interface with minimal glue logic to microprocessors/microcontrollers for high performance read operations. the devices offer complete compatibility with the jedec 42.4 single-power-supply flash command set standard . commands are written to the command register using standard mi - croprocessor write timings. reading data out of th e device are similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device status bit dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the devices are fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the devices also offer three types of data protection at the sector level. the sector lock/unlock command sequence disables or re-enables both program and erase operations in any sector. when at v il , wp# locks the highest two sectors. finally, when a cc is at v il , all sectors are locked. the devices offer two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. s29ns032j bank a sectors bank b, c & d sectors quantity size quantity size 4 8 kwords 16 32 kwords 15 32 kwords 8 mbits total 24 mbits total s29ns016j bank a sectors bank b, c & d sectors quantity size quantity size 4 8 kwords 8 32 kwords 7 32 kwords 4 mbits total 12 mbits total
4S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet product selector guide block diagram note: a max indicates the highest order address bit. part number s29ns128j, s29ns064j, s29n032j, 29ns016j burst frequency 66 mhz 54 mhz speed option 0p 0l max initial synchronous access time, ns (t iacc ) 71 87.5 max burst access time, ns (t bacc ) 11 13.5 max asynchronous access time, ns (t acc ) 65 70 max ce# access time, ns (t ce ) max oe# access time, ns (t oe ) 11 13.5 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# a cc ce# oe# a/dq15?a/dq0 data latch y-gating cell matrix address latch a/dq15?a/dq0 a max ?a16 rdy buffer rdy burst state control burst address counter avd# clk a max ?a0
march 22, 2006 S29NS-J_00_a10 S29NS-J 5 data sheet block diagram of simultaneous operation circuit notes: 1. a15?a0 are multiplexed with dq15?dq0. 2. amax indicates the highest order address bit. v cc v ss acc bank b address reset# we# ce# avd# dq15?dq0 clk s tat e control & command register bank b x-decoder y-decoder latches and control logic bank a x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15? dq0 bank c y-decoder x-decoder latches and control logic bank d y-decoder x-decoder latches and control logic oe# oe# oe# oe# status control ?a max ?a0 ?a max ?a0 ?a max ?a0 ?a max ?a0? ?a max ?a0 bank c address bank d address bank a address rdy
6S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet connection diagram a1 rdy a2 a21 a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 a22 b1 v cc b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 wp# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc nc nc nc nc s29ns128j 48 -ball very thin fbga (vdc048) to p v i e w, b a l l s fa c i n g d o w n
march 22, 2006 S29NS-J_00_a10 S29NS-J 7 data sheet connection diagram a1 rdy a2 a21 a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 nc b1 v cc b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 wp# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc s29ns064j 44 -ball very thin fbga (vdd044) to p v i ew, b a l ls fa c i n g d o w n
8S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet connection diagram a1 rdy a2 nc a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 nc b1 v cc b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 wp# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc s29ns032j 44 -ball very thin fbga (vde 044) to p v i ew, b a l ls fa c i n g d o w n
march 22, 2006 S29NS-J_00_a10 S29NS-J 9 data sheet connection diagram a1 rdy a2 nc a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 nc b1 v cc b2 a16 b3 nc b4 avd# b5 nc b6 reset# b7 wp# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc s29ns016j 44 -ball very thin fbga (vde044) to p v i ew, b a l ls fa c i n g d o w n
10 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet input/output descriptions a22?a16 = address inputs, s29ns128j a21?a16 = address inputs, s29ns064j a20?a16 = address inputs, s29ns032j a19?a16 = address inputs, s29ns016j a/dq15? a/dq0 = multiplexed address/data input/output ce# = chip enable input. asynchro nous relative to clk for the burst mode. oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v cc = device power supply (1.7 v?1.95 v). gnd = ground nc = no connect; not connected internally rdy = ready output; indicates the status of the burst read. v ol = data invalid. v oh = data valid. clk = the first rising edge of clk in conjunction with avd# low latches address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access. avd# = address valid input. indicates to device that the valid address is present on the addr ess inputs (address bits a15? a0 are multiplexed, address bits a22?a16 are address only). v il = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of clk. v ih = device ignores address inputs reset# = hardware reset input. v il = device resets and returns to reading array data wp# = hardware write protect input. v il = disables writes to sa257?258 (s29ns128j), sa129?130 (s29ns064j), sa65?66 (s29ns032j), or sa33-34 (s29ns016j). should be at v ih for all other conditions. a cc = at 12 v, accelerates programming; automatically places device in unlock bypass mode. at v il , disables program and erase functions. should be at v ih for all other conditions.
march 22, 2006 S29NS-J_00_a10 S29NS-J 11 data sheet logic symbol 16 a/dq15? a/dq0 a max ?a16 ce# oe# we# reset# clk rdy avd# wp# a cc a max indicates the highest order address bit.
12 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ordering information the order number (valid combination) is formed by the following: s29ns 128 j 0l ba w 00 3 packing type 0= tray 2 = 7 inch tape and reel 3 = 13 inch tape and reel additional ordering options 00 = standard configuration temperature range w = wireless (?25 c to +85 c) package type ba = very thin fine-pitch bga lead (pb)-free compliant package bf = very thin fine-pitch bga lead (pb)-free package bj = very thin fine-pitch bga lead (pb)-free lf35 package clock rate 0p = 66 mhz 0l = 54 mhz process technology j = 110 nm floating gate technology density 128 = 128 megabit (8 m x 16-bit) 064 = 64 megabit (4 m x 16-bit) 032 = 32 megabit (2 m x 16-bit) 016 = 16 megabit (1 m x 16-bit) device s29ns = simultaneous read/write, burst mode flash memory with multiplexed i/o 1.8-volt operation
march 22, 2006 S29NS-J_00_a10 S29NS-J 13 data sheet valid combinations the following configurations are planned to be supported for this device. contact your local span - sion sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: for industrial temperature range, contact your local sales office. valid combinations bga package order number packing type package marking package density speed s29ns128j0pbaw00 0, 2 or 3 ns128j0pbaw00 pb-free compliant 128 66 mhz s29ns128j0pbjw00 0, 2 or 3 ns128j0pbjw00 pb-free, lf35 s29ns128j0pbfw00 0, 2 or 3 ns128j0pbfw00 pb-free s29ns064j0pbaw00 0, 2 or 3 ns064j0pbaw00 pb-free compliant 64 s29ns064j0pbjw00 0, 2 or 3 ns064j0pbjw00 pb-free, lf35 s29ns064j0pbfw00 0, 2 or 3 ns064j0pbfw00 pb-free s29ns032j0pbjw00 0, 2 or 3 ns032j0pbjw00 pb-free, lf35 32 s29ns032j0pbfw00 0, 2 or 3 ns032j0pbfw00 pb-free s29ns016j0pbjw00 0, 2 or 3 ns016j0pbjw00 pb-free, lf35 16 s29ns016j0pbfw00 0, 2 or 3 ns016j0pbfw00 pb-free s29ns128j0lbaw00 0, 2 or 3 ns128j0lbaw00 pb-free compliant 128 54 mhz s29ns128j0lbjw00 0, 2 or 3 ns128j0lbjw00 pb-free, lf35 s29ns128j0lbfw00 0, 2 or 3 ns128j0lbfw00 pb-free s29ns064j0lbaw00 0, 2 or 3 ns064j0lbaw00 pb-free compliant 64 s29ns064j0lbjw00 0, 2 or 3 ns064j0lbjw00 pb-free, lf35 s29ns064j0lbfw00 0, 2 or 3 ns064j0lbfw00 pb-free s29ns032j0lbjw00 0, 2 or 3 ns032j0lbjw00 pb-free, lf35 32 s29ns032j0lbfw00 0, 2 or 3 ns032j0lbfw00 pb-free s29ns016j0lbjw00 0, 2 or 3 ns016j0lbjw00 pb-free, lf35 16 s29ns016j0lbfw00 0, 2 or 3 ns016j0lbfw00 pb-free
14 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addres - sable memory location. the register is composed of latches that store the commands, along with the address and data information needed to exec ute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic 0, h = logic 1, x = don?t care. requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must assert a valid address on a/dq15?a/dq0 and a max ?a16, while avd# and ce# are at v il . we# should remain at v ih . note that clk must remain at v il during asynchronous read operations. the rising edge of avd# latches the address, after which the system can drive oe# to v il . the data will appear on a/dq15?a/dq0. (see figure 13 .) since the memory array is di vided into four bank s, each bank remains enabled for read ac - cess until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. requirements for synchronous (burst) read operation the device is capable of seven different burst read modes (see ta b l e 11 ): continuous burst read; 8-, 16-, and 32-word linear burst reads with wrap around; and 8-, 16-, and 32-word linear burst reads without wrap around. operation ce# oe# we# a max ?16 a/dq15?0 reset# clk avd# asynchronous read l l h addr in i/o h l write l h l addr in i/o h h/l standby (ce#) h x x x high z h h/l x hardware reset x x x x high z l x x burst read operations load starting burst address l h h addr in addr in h advance burst to next address with appropriate data presented on the data bus l l h x burst data out h h terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle l h h x i/o h
march 22, 2006 S29NS-J_00_a10 S29NS-J 15 data sheet continuous burst when the device first powers up, it is enabled for asynchronous read operation. the device will automatically be enabled for burst mode and addresses will be latched on the first rising edge on the clk input, while avd# is held low for one clock cycle. prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst session. the system would then write th e set configuration register command sequence. the initial word is output t iacc after the rising edge of the first clk cycle. subsequent words are output t bacc after the rising edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fi xed internal address boundary that occurs every 64 words, starting at a ddress 00003fh. the transition from the high - est address to 000000h is also a boundary crossing . during a boundary crossing, there is a two-cycle latency between the valid read at address 00003eh and the valid read at address 00003fh (or between addresses offset from these values by the same multiple of 64 words). rdy is deasserted during the two-cycle latency, and it is reasserted in the third cycle to indicate that the data at address 00003fh (or offset from 3fh by a multiple of 64 words) is ready. see figure 21 . the device will continue to output continuous, se quential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system asserts ce# high, reset# low, or avd# low in conjunction with a new address. see ta b l e 1 . the reset com - mand does not terminate the burst read operation. if the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as described above. if the host system crosses the bank boundary while the device is pr ogramming or erasing, the device will provide asynchronous read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and avd# pulse. if the clock frequency is less than 6 mhz during a burst mode operation, additional latencies will occur. rdy indicates the length of the latency by pulsing low. 8-, 16-, and 32-word linear burst with wrap around these three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are deter - mined by the group within which the starting addr ess falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see ta b l e 2 .)
16 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet as an example: if the starting address in the 8- word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence woul d be 39-3a-3b-3c-3d-3e-3f-38h. the burst se - quence begins with the starting address written to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address writte n to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the ad - dress pointer does not cross the boundary th at occurs every 64 words; thus, no wait states are inserted (except during the initial access). 8-, 16-, and 32-word linear burst without wrap around in these modes, a fixed number of words (predefi ned as 8,16,or 32 words) are read from con - secutive addresses starting with the initial word, which is written to the device. when the number of words has been read completely, the burst read operation stops and the rdy output goes low. there is no group limitation and is different from the linear burst with wrap around. see ta b l e 11 and ta b l e 18 for the command of setting the 8-, 16-, and 32- word burst without wrap around. as an example, for 8-word length burst read, if th e starting address written to the device is 39h, the burst sequence would be 39-3a-3b-3c-3d-3e- 3f-40h, and the read operation will be termi - nated at 40h. in a similar fashion, the 16-wor d and 32-word modes begin their burst sequence on the starting address written to the device, and continuously read to the predefined word length, 16 or 32 words. the operation is similar to the continuous burst, but will stop the operation at fixed word length. it is possible the device crosses the fixed internal address boundary that occurs every 64 words during burst read; a latency occurs before data appears for the next address and rdy is pulsing low. if the host system crosses the bank boundary, the device will react in the same manner as in the continuous burst. if the clock frequency is less than 6 mhz during a burst mode operation, additional latencies will occur. rdy indicates the length of the latency by pulsing low. programmable wait state the programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after avd# is driven active before data will be available. upon power up, the device defaults to the maximum of seven total cy cles. the total number of wait states is program - mable from two to seven cycles. the wait state command sequence requires three cycles; after the two unlock cycles, the third cycle address should be written according to the desired wait state as shown in ta b l e 11 . address bits a11-a0 should be set to 555h, while addresses bits a17-a12 set the wait state. for further details, see ?set configuration register command sequence? . ta b l e 2 . burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h, 18-1fh... 16-word 16 words 0-fh, 10-1fh, 20-2fh, 30-3fh... 32-word 32 words 00-1fh, 20-3fh, 40-5fh, 60-7fh...
march 22, 2006 S29NS-J_00_a10 S29NS-J 17 data sheet handshaking feature the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial word of burst data is ready to be read. the host system should use the wait state command sequence to set the number of wait states for optimal burst mode oper - ation (03h for 54 and 66 mhz clock). the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. simultaneous read/write operations with zero latency this device is capable of reading data from on e bank of memory while programming or erasing in one of the other three banks of memory. an erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). fig - ure 24 shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase cur - rent specifications. writing commands/command sequences the device has inputs/outputs that accept both address and data information. to write a com - mand or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih . when writing commands or data. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. an erase operation can erase one sector, multiple sectors, or the entire device. table 7 indicates the address space that each sector occupies. the device address space is divided into four banks: bank a contains both 8 kword boot sectors in addition to 32 kword sectors, while banks b, c, and d contain only 32 kword sectors. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. refer to the dc characteristics table for write mode current specifications. the ac characteristics section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the a cc input. this function is primarily intended to allow faster manufacturing throughp ut at the factory. if the system asserts v id on this input, the device automatically enters the aforementioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v id from the a cc input returns the device to normal operation. autoselect functions if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the au - toselect functions and autoselect command sequence sections for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the outputs are placed in the high impedance state, inde pendent of the oe# input.
18 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, be fore it is read y to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enters this mode when addresses remain stable for t acc + 60 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control si gnals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset input the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase operation, the device requires a time of t readyw (during embedded algorithms) before the device is ready to read data again. if reset# is as - serted when a program or erase operation is not executing, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the ac characteristics tables for reset# parameters an d to 14 for the timing diagram. v cc power-up and powe r-down sequencing the device imposes no restrictions on v cc power-up or power-down sequencing. asserting re - set# to v il is required during the entire v cc power sequence until the respective supplies reach their operating voltages. once v cc attains its operating voltage, de-assertion of reset# to v ih is permitted. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to ta b l e 18 for command definitions). the device offers three types of data protection at the sector level:
march 22, 2006 S29NS-J_00_a10 S29NS-J 19 data sheet ? the sector lock/unlock command sequence disables or re-enables both program and erase operations in any sector. ? when wp# is at v il , ?sa257 and sa258 are locked (s29ns128j) ?sa129 and sa130 are locked (s29ns064j) ?sa65 and sa66 are locked (s29ns032j) ?sa33 and sa34 are locked (s29ns016j) ? when a cc is at v il , all sectors are locked. wp# boot sector protection the wp# signal will be latched at a specific time in the embedded program or erase sequence. to prevent a write to the top two sectors, wp# must be asserted (wp#=v il ) on the last write cycle of the embedded sequence (i.e., 4th write cycle in embedded program, 6th write cycle in embed - ded erase). if using the unlock bypass feature: on the 2nd program cycle, after the unlock bypass command is written, the wp# signal must be asserted on the 2nd cycle. if selecting multiple sectors for erasure: the wp # protection status is latched only on the 6th write cycle of the embedded sector erase command sequence when the first sector is selected. if additional sectors are selected for erasure, they are subject to the wp# status that was latched on the 6th write cycle of the command sequence. the following hardware data prot ection measures prevent accide ntal erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any writ e cycles. this prot ects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one.
20 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software inter - rogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-indepen - dent, and forward- and backward-c ompatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when th e system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 3 ? 6 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 3 ? 6 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specification and cfi publication 100, available through the world wide web at http://www.amd.com /flash/cfi. alternatively, contact your local spansion sales office for copies of these documents. table 3. cfi query identification string addresses data description s29ns128j s29ns064j s29ns032j s29ns016j 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 4. system interface string (sheet 1 of 2) addresses data description s29ns128j s29ns064j s29ns032j s29ns016j 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h a cc min. voltage (00h = no a cc pin present) refer to 4dh 1eh 0000h a cc max. voltage (00h = no a cc pin present) refer to 4eh 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical
march 22, 2006 S29NS-J_00_a10 S29NS-J 21 data sheet 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 5. device geometry definition addresses data description s29ns128j s29ns064j s29ns032j s29ns016j 27h 0018h 0017h 0016h 0015h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0002h number of erase block regions within device 2dh 2eh 2fh 30h 00feh 0000h 0000h 0001h 007eh 0000h 0000h 0001h 003eh 0000h 0000h 0001h 001eh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specific ation or cfi publication 100) 31h 32h 33h 34h 0003h 0000h 0040h 0000h erase block region 2 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information ta b l e 6 . primary vendor-specific extended query (sheet 1 of 2) addresses data description s29ns128j s29ns064j s29ns032j s29ns016j 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0000h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0005h sector protect/unprotect scheme 05 = 29bds/n128 mode 4ah 00c0h 0060h 0030h 0018h simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv table 4. system interface string (sheet 2 of 2) addresses data description s29ns128j s29ns064j s29ns032j s29ns016j
22 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0003h top/bottom boot sector flag 0001h = top/middle boot device, 0002h = bottom boot device, 03h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0040h 0020h 0010h 0008h bank d region information. x = number of sectors in bank 59h 0040h 0020h 0010h 0008h bank c region information. x = number of sectors in bank 5ah 0040h 0020h 0010h 0008h bank b region information. x = number of sectors in bank 5bh 0043h 0023h 0013h 0008h bank a region information. x = number of sectors in bank 5ch 0002h process technology. 00h = 230 nm, 01h = 170 nm, 02h = 130 nm/ 110 nm table 6. primary vendor-specific extended query (sheet 2 of 2) addresses data description s29ns128j s29ns064j s29ns032j s29ns016j
march 22, 2006 S29NS-J_00_a10 S29NS-J 23 data sheet ta b l e 7 . sector address table, s29ns128j (sheet 1 of 4) sector sector size address range sector sector size address range bank d sa0 32 kwords 000000h?007fffh sa32 32 kwords 100000h?107fffh sa1 32 kwords 008000h?00ffffh sa33 32 kwords 108000h?10ffffh sa2 32 kwords 010000h?017fffh sa34 32 kwords 110000h?117fffh sa3 32 kwords 018000h?01ffffh sa35 32 kwords 118000h?11ffffh sa4 32 kwords 020000h?027fffh sa36 32 kwords 120000h?127fffh sa5 32 kwords 028000h?02ffffh sa37 32 kwords 128000h?12ffffh sa6 32 kwords 030000h?037fffh sa38 32 kwords 130000h?137fffh sa7 32 kwords 038000h?03ffffh sa39 32 kwords 138000h?13ffffh sa8 32 kwords 040000h?047fffh sa40 32 kwords 140000h?147fffh sa9 32 kwords 048000h?04ffffh sa41 32 kwords 148000h?14ffffh sa10 32 kwords 050000h?057fffh sa42 32 kwords 150000h?157fffh sa11 32 kwords 058000h?05ffffh sa43 32 kwords 158000h?15ffffh sa12 32 kwords 060000h?067fffh sa44 32 kwords 160000h?167fffh sa13 32 kwords 068000h?06ffffh sa45 32 kwords 168000h?16ffffh sa14 32 kwords 070000h?077fffh sa46 32 kwords 170000h?177fffh sa15 32 kwords 078000h?07ffffh sa47 32 kwords 178000h?17ffffh sa16 32 kwords 080000h?087fffh sa48 32 kwords 180000h?187fffh sa17 32 kwords 088000h?08ffffh sa49 32 kwords 188000h?18ffffh sa18 32 kwords 090000h?097fffh sa50 32 kwords 190000h?197fffh sa19 32 kwords 098000h?09ffffh sa51 32 kwords 198000h?19ffffh sa20 32 kwords 0a0000h?0a7fffh sa52 32 kwords 1a0000h?1a7fffh sa21 32 kwords 0a8000h?0affffh sa53 32 kwords 1a8000h?1affffh sa22 32 kwords 0b0000h?0b7fffh sa54 32 kwords 1b0000h?1b7fffh sa23 32 kwords 0b8000h?0bffffh sa55 32 kwords 1b8000h?1bffffh sa24 32 kwords 0c0000h?0c7fffh sa56 32 kwords 1c0000h?1c7fffh sa25 32 kwords 0c8000h?0cffffh sa57 32 kwords 1c8000h?1cffffh sa26 32 kwords 0d0000h?0d7fffh sa58 32 kwords 1d0000h?1d7fffh sa27 32 kwords 0d8000h?0dffffh sa59 32 kwords 1d8000h?1dffffh sa28 32 kwords 0e0000h?0e7fffh sa60 32 kwords 1e0000h?1e7fffh sa29 32 kwords 0e8000h?0effffh sa61 32 kwords 1e8000h?1effffh sa30 32 kwords 0f0000h?0f7fffh sa62 32 kwords 1f0000h?1f7fffh sa31 32 kwords 0f8000h?0fffffh sa63 32 kwords 1f8000h?1fffffh
24 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet bank c sa64 32 kwords 200000h?207fffh sa96 32 kwords 300000h?307fffh sa65 32 kwords 208000h?20ffffh sa97 32 kwords 308000h?30ffffh sa66 32 kwords 210000h?217fffh sa98 32 kwords 310000h?317fffh sa67 32 kwords 218000h?21ffffh sa99 32 kwords 318000h?31ffffh sa68 32 kwords 220000h?227fffh sa100 32 kwords 320000h?327fffh sa69 32 kwords 228000h?22ffffh sa101 32 kwords 328000h?32ffffh sa70 32 kwords 230000h?237fffh sa102 32 kwords 330000h?337fffh sa71 32 kwords 238000h?23ffffh sa103 32 kwords 338000h?33ffffh sa72 32 kwords 240000h?247fffh sa104 32 kwords 340000h?347fffh sa73 32 kwords 248000h?24ffffh sa105 32 kwords 348000h?34ffffh sa74 32 kwords 250000h?257fffh sa106 32 kwords 350000h?357fffh sa75 32 kwords 258000h?25ffffh sa107 32 kwords 358000h?35ffffh sa76 32 kwords 260000h?267fffh sa108 32 kwords 360000h?367fffh sa77 32 kwords 268000h?26ffffh sa109 32 kwords 368000h?36ffffh sa78 32 kwords 270000h?277fffh sa110 32 kwords 370000h?377fffh sa79 32 kwords 278000h?27ffffh sa111 32 kwords 378000h?37ffffh sa80 32 kwords 280000h?287fffh sa112 32 kwords 380000h?387fffh sa81 32 kwords 288000h?28ffffh sa113 32 kwords 388000h?38ffffh sa82 32 kwords 290000h?297fffh sa114 32 kwords 390000h?397fffh sa83 32 kwords 298000h?29ffffh sa115 32 kwords 398000h?39ffffh sa84 32 kwords 2a0000h?2a7fffh sa116 32 kwords 3a0000h?3a7fffh sa85 32 kwords 2a8000h?2affffh sa117 32 kwords 3a8000h?3affffh sa86 32 kwords 2b0000h?2b7fffh sa118 32 kwords 3b0000h?3b7fffh sa87 32 kwords 2b8000h?2bffffh sa119 32 kwords 3b8000h?3bffffh sa88 32 kwords 2c0000h?2c7fffh sa120 32 kwords 3c0000h?3c7fffh sa89 32 kwords 2c8000h?2cffffh sa121 32 kwords 3c8000h?3cffffh sa90 32 kwords 2d0000h?2d7fffh sa122 32 kwords 3d0000h?3d7fffh sa91 32 kwords 2d8000h?2dffffh sa123 32 kwords 3d8000h?3dffffh sa92 32 kwords 2e0000h?2e7fffh sa124 32 kwords 3e0000h?3e7fffh sa93 32 kwords 2e8000h?2effffh sa125 32 kwords 3e8000h?3effffh sa94 32 kwords 2f0000h?2f7fffh sa126 32 kwords 3f0000h?3f7fffh sa95 32 kwords 2f8000h?2fffffh sa127 32 kwords 3f8000h?3fffffh table 7. sector address table, s29ns128j (sheet 2 of 4) sector sector size address range sector sector size address range
march 22, 2006 S29NS-J_00_a10 S29NS-J 25 data sheet bank b sa128 32 kwords 400000h?407fffh sa160 32 kwords 500000h?507fffh sa129 32 kwords 408000h?40ffffh sa161 32 kwords 508000h?50ffffh sa130 32 kwords 410000h?417fffh sa162 32 kwords 510000h?517fffh sa131 32 kwords 418000h?41ffffh sa163 32 kwords 518000h?51ffffh sa132 32 kwords 420000h?427fffh sa164 32 kwords 520000h?527fffh sa133 32 kwords 428000h?42ffffh sa165 32 kwords 528000h?52ffffh sa134 32 kwords 420000h?427fffh sa166 32 kwords 530000h?537fffh sa135 32 kwords 438000h?43ffffh sa167 32 kwords 538000h?53ffffh sa136 32 kwords 430000h?437fffh sa168 32 kwords 540000h?547fffh sa137 32 kwords 448000h?44ffffh sa169 32 kwords 548000h?54ffffh sa138 32 kwords 450000h?457fffh sa170 32 kwords 550000h?557fffh sa139 32 kwords 458000h?45ffffh sa171 32 kwords 558000h?55ffffh sa140 32 kwords 460000h?467fffh sa172 32 kwords 560000h?567fffh sa141 32 kwords 468000h?46ffffh sa173 32 kwords 568000h?56ffffh sa142 32 kwords 470000h?477fffh sa174 32 kwords 570000h?577fffh sa143 32 kwords 478000h?47ffffh sa175 32 kwords 578000h?57ffffh sa144 32 kwords 480000h?487fffh sa176 32 kwords 580000h?587fffh sa145 32 kwords 488000h?48ffffh sa177 32 kwords 588000h?58ffffh sa146 32 kwords 490000h?497fffh sa178 32 kwords 590000h?597fffh sa147 32 kwords 498000h?49ffffh sa179 32 kwords 598000h?59ffffh sa148 32 kwords 4a0000h?4a7fffh sa180 32 kwords 5a0000h?5a7fffh sa149 32 kwords 4a8000h?4affffh sa181 32 kwords 5a8000h?5affffh sa150 32 kwords 4b0000h?4b7fffh sa182 32 kwords 5b0000h?5b7fffh sa151 32 kwords 4b8000h?4bffffh sa183 32 kwords 5b8000h?5bffffh sa152 32 kwords 4c0000h?4c7fffh sa184 32 kwords 5c0000h?5c7fffh sa153 32 kwords 4c8000h?4cffffh sa185 32 kwords 5c8000h?5cffffh sa154 32 kwords 4d0000h?4d7fffh sa186 32 kwords 5d0000h?5d7fffh sa155 32 kwords 4d8000h?4dffffh sa187 32 kwords 5d8000h?5dffffh sa156 32 kwords 4e0000h?4e7fffh sa188 32 kwords 5e0000h?5e7fffh sa157 32 kwords 4e8000h?4effffh sa189 32 kwords 5e8000h?5effffh sa158 32 kwords 4f0000h?4f7fffh sa190 32 kwords 5f0000h?5f7fffh sa159 32 kwords 4f8000h?4fffffh sa191 32 kwords 5f8000h?5fffffh table 7. sector address table, s29ns128j (sheet 3 of 4) sector sector size address range sector sector size address range
26 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet bank a sa192 32 kwords 600000h?607fffh sa224 32 kwords 700000h?707fffh sa193 32 kwords 608000h?60ffffh sa225 32 kwords 708000h?70ffffh sa194 32 kwords 610000h?617fffh sa226 32 kwords 710000h?717fffh sa195 32 kwords 618000h?61ffffh sa227 32 kwords 718000h?71ffffh sa196 32 kwords 620000h?627fffh sa228 32 kwords 720000h?727fffh sa197 32 kwords 628000h?62ffffh sa229 32 kwords 728000h?72ffffh sa198 32 kwords 630000h?637fffh sa230 32 kwords 730000h?737fffh sa199 32 kwords 638000h?63ffffh sa231 32 kwords 738000h?73ffffh sa200 32 kwords 640000h?647fffh sa232 32 kwords 740000h?747fffh sa201 32 kwords 648000h?64ffffh sa233 32 kwords 748000h?74ffffh sa202 32 kwords 650000h?657fffh sa234 32 kwords 750000h?757fffh sa203 32 kwords 658000h?65ffffh sa235 32 kwords 758000h?75ffffh sa204 32 kwords 660000h?667fffh sa236 32 kwords 760000h?767fffh sa205 32 kwords 668000h?66ffffh sa237 32 kwords 768000h?76ffffh sa206 32 kwords 670000h?677fffh sa238 32 kwords 770000h?777fffh sa207 32 kwords 678000h?67ffffh sa239 32 kwords 778000h?77ffffh sa208 32 kwords 680000h?687fffh sa240 32 kwords 780000h?787fffh sa209 32 kwords 688000h?68ffffh sa241 32 kwords 788000h?78ffffh sa210 32 kwords 690000h?697fffh sa242 32 kwords 790000h?797fffh sa211 32 kwords 698000h?69ffffh sa243 32 kwords 798000h?79ffffh sa212 32 kwords 6a0000h?6a7fffh sa244 32 kwords 7a0000h?7a7fffh sa213 32 kwords 6a8000h?6affffh sa245 32 kwords 7a8000h?7affffh sa214 32 kwords 6b0000h?6b7fffh sa246 32 kwords 7b0000h?7b7fffh sa215 32 kwords 6b8000h?6bffffh sa247 32 kwords 7b8000h?7bffffh sa216 32 kwords 6c0000h?6c7fffh sa248 32 kwords 7c0000h?7c7fffh sa217 32 kwords 6c8000h?6cffffh sa249 32 kwords 7c8000h?7cffffh sa218 32 kwords 6d0000h?6d7fffh sa250 32 kwords 7d0000h?7d7fffh sa219 32 kwords 6d8000h?6dffffh sa251 32 kwords 7d8000h?7dffffh sa220 32 kwords 6e0000h?6e7fffh sa252 32 kwords 7e0000h?7e7fffh sa221 32 kwords 6e8000h?6effffh sa253 32 kwords 7e8000h?7effffh sa222 32 kwords 6f0000h?6f7fffh sa254 32 kwords 7f0000h?7f7fffh sa223 32 kwords 6f8000h?6fffffh sa255 8 kwords 7f8000h?7f9fffh sa256 8 kwords 7fa000h?7fbfffh sa257 8 kwords 7fc000h?7fdfffh sa258 8 kwords 7fe000h?7fffffh table 7. sector address table, s29ns128j (sheet 4 of 4) sector sector size address range sector sector size address range
march 22, 2006 S29NS-J_00_a10 S29NS-J 27 data sheet ta b l e 8 . sector address table, s29ns064j (sheet 1 of 4) sector sector size address range bank d sa0 32 kwords 000000h?007fffh sa1 32 kwords 008000h?00ffffh sa2 32 kwords 010000h?017fffh sa3 32 kwords 018000h?01ffffh sa4 32 kwords 020000h?027fffh sa5 32 kwords 028000h?02ffffh sa6 32 kwords 030000h?037fffh sa7 32 kwords 038000h?03ffffh sa8 32 kwords 040000h?047fffh sa9 32 kwords 048000h?04ffffh sa10 32 kwords 050000h?057fffh sa11 32 kwords 058000h?05ffffh sa12 32 kwords 060000h?067fffh sa13 32 kwords 068000h?06ffffh sa14 32 kwords 070000h?077fffh sa15 32 kwords 078000h?07ffffh sa16 32 kwords 080000h?087fffh sa17 32 kwords 088000h?08ffffh sa18 32 kwords 090000h?097fffh sa19 32 kwords 098000h?09ffffh sa20 32 kwords 0a0000h?0a7fffh sa21 32 kwords 0a8000h?0affffh sa22 32 kwords 0b0000h?0b7fffh sa23 32 kwords 0b8000h?0bffffh sa24 32 kwords 0c0000h?0c7fffh sa25 32 kwords 0c8000h?0cffffh sa26 32 kwords 0d0000h?0d7fffh sa27 32 kwords 0d8000h?0dffffh sa28 32 kwords 0e0000h?0e7fffh sa29 32 kwords 0e8000h?0effffh sa30 32 kwords 0f0000h?0f7fffh sa31 32 kwords 0f8000h?0fffffh
28 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet bank c sa32 32 kwords 100000h?107fffh sa33 32 kwords 108000h?10ffffh sa34 32 kwords 110000h?117fffh sa35 32 kwords 118000h?11ffffh sa36 32 kwords 120000h?127fffh sa37 32 kwords 128000h?12ffffh sa38 32 kwords 130000h?137fffh sa39 32 kwords 138000h?13ffffh sa40 32 kwords 140000h?147fffh sa41 32 kwords 148000h?14ffffh sa42 32 kwords 150000h?157fffh sa43 32 kwords 158000h?15ffffh sa44 32 kwords 160000h?167fffh sa45 32 kwords 168000h?16ffffh sa46 32 kwords 170000h?177fffh sa47 32 kwords 178000h?17ffffh sa48 32 kwords 180000h?187fffh sa49 32 kwords 188000h?18ffffh sa50 32 kwords 190000h?197fffh sa51 32 kwords 198000h?19ffffh sa52 32 kwords 1a0000h?1a7fffh sa53 32 kwords 1a8000h?1affffh sa54 32 kwords 1b0000h?1b7fffh sa55 32 kwords 1b8000h?1bffffh sa56 32 kwords 1c0000h?1c7fffh sa57 32 kwords 1c8000h?1cffffh sa58 32 kwords 1d0000h?1d7fffh sa59 32 kwords 1d8000h?1dffffh sa60 32 kwords 1e0000h?1e7fffh sa61 32 kwords 1e8000h?1effffh sa62 32 kwords 1f0000h?1f7fffh sa63 32 kwords 1f8000h?1fffffh table 8. sector address table, s29ns064j (sheet 2 of 4) sector sector size address range
march 22, 2006 S29NS-J_00_a10 S29NS-J 29 data sheet bank b sa64 32 kwords 200000h?207fffh sa65 32 kwords 208000h?20ffffh sa66 32 kwords 210000h?217fffh sa67 32 kwords 218000h?21ffffh sa68 32 kwords 220000h?227fffh sa69 32 kwords 228000h?22ffffh sa70 32 kwords 230000h?237fffh sa71 32 kwords 238000h?23ffffh sa72 32 kwords 240000h?247fffh sa73 32 kwords 248000h?24ffffh sa74 32 kwords 250000h?257fffh sa75 32 kwords 258000h?25ffffh sa76 32 kwords 260000h?267fffh sa77 32 kwords 268000h?26ffffh sa78 32 kwords 270000h?277fffh sa79 32 kwords 278000h?27ffffh sa80 32 kwords 280000h?287fffh sa81 32 kwords 288000h?28ffffh sa82 32 kwords 290000h?297fffh sa83 32 kwords 298000h?29ffffh sa84 32 kwords 2a0000h?2a7fffh sa85 32 kwords 2a8000h?2affffh sa86 32 kwords 2b0000h?2b7fffh sa87 32 kwords 2b8000h?2bffffh sa88 32 kwords 2c0000h?2c7fffh sa89 32 kwords 2c8000h?2cffffh sa90 32 kwords 2d0000h?2d7fffh sa91 32 kwords 2d8000h?2dffffh sa92 32 kwords 2e0000h?2e7fffh sa93 32 kwords 2e8000h?2effffh sa94 32 kwords 2f0000h?2f7fffh sa95 32 kwords 2f8000h?2fffffh table 8. sector address table, s29ns064j (sheet 3 of 4) sector sector size address range
30 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet bank a sa96 32 kwords 300000h?307fffh sa97 32 kwords 308000h?30ffffh sa98 32 kwords 310000h?317fffh sa99 32 kwords 318000h?31ffffh sa100 32 kwords 320000h?327fffh sa101 32 kwords 328000h?32ffffh sa102 32 kwords 330000h?337fffh sa103 32 kwords 338000h?33ffffh sa104 32 kwords 340000h?347fffh sa105 32 kwords 348000h?34ffffh sa106 32 kwords 350000h?357fffh sa107 32 kwords 358000h?35ffffh sa108 32 kwords 360000h?367fffh sa109 32 kwords 368000h?36ffffh sa110 32 kwords 370000h?377fffh sa111 32 kwords 378000h?37ffffh sa112 32 kwords 380000h?387fffh sa113 32 kwords 388000h?38ffffh sa114 32 kwords 390000h?397fffh sa115 32 kwords 398000h?39ffffh sa116 32 kwords 3a0000h?3a7fffh sa117 32 kwords 3a8000h?3affffh sa118 32 kwords 3b0000h?3b7fffh sa119 32 kwords 3b8000h?3bffffh sa120 32 kwords 3c0000h?3c7fffh sa121 32 kwords 3c8000h?3cffffh sa122 32 kwords 3d0000h?3d7fffh sa123 32 kwords 3d8000h?3dffffh sa124 32 kwords 3e0000h?3e7fffh sa125 32 kwords 3e8000h?3effffh sa126 32 kwords 3f0000h?3f7fffh sa127 8 kwords 3f8000h?3f9fffh sa128 8 kwords 3fa000h?3fbfffh sa129 8 kwords 3fc000h?3fdfffh sa130 8 kwords 3fe000h?3fffffh table 8. sector address table, s29ns064j (sheet 4 of 4) sector sector size address range
march 22, 2006 S29NS-J_00_a10 S29NS-J 31 data sheet ta b l e 9 . sector address table, s29ns032j (sheet 1 of 2) sector sector size address range bank d sa0 32 kwords 000000h?007fffh sa1 32 kwords 008000h?00ffffh sa2 32 kwords 010000h?017fffh sa3 32 kwords 018000h?01ffffh sa4 32 kwords 020000h?027fffh sa5 32 kwords 028000h?02ffffh sa6 32 kwords 030000h?037fffh sa7 32 kwords 038000h?03ffffh sa8 32 kwords 040000h?047fffh sa9 32 kwords 048000h?04ffffh sa10 32 kwords 050000h?057fffh sa11 32 kwords 058000h?05ffffh sa12 32 kwords 060000h?067fffh sa13 32 kwords 068000h?06ffffh sa14 32 kwords 070000h?077fffh sa15 32 kwords 078000h?07ffffh bank c sa16 32 kwords 080000h?087fffh sa17 32 kwords 088000h?08ffffh sa18 32 kwords 090000h?097fffh sa19 32 kwords 098000h?09ffffh sa20 32 kwords 0a0000h?0a7fffh sa21 32 kwords 0a8000h?0affffh sa22 32 kwords 0b0000h?0b7fffh sa23 32 kwords 0b8000h?0bffffh sa24 32 kwords 0c0000h?0c7fffh sa25 32 kwords 0c8000h?0cffffh sa26 32 kwords 0d0000h?0d7fffh sa27 32 kwords 0d8000h?0dffffh sa28 32 kwords 0e0000h?0e7fffh sa29 32 kwords 0e8000h?0effffh sa30 32 kwords 0f0000h?0f7fffh sa31 32 kwords 0f8000h?0fffffh
32 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet bank b sa32 32 kwords 100000h?107fffh sa33 32 kwords 108000h?10ffffh sa34 32 kwords 110000h?117fffh sa35 32 kwords 118000h?11ffffh sa36 32 kwords 120000h?127fffh sa37 32 kwords 128000h?12ffffh sa38 32 kwords 130000h?137fffh sa39 32 kwords 138000h?13ffffh sa40 32 kwords 140000h?147fffh sa41 32 kwords 148000h?14ffffh sa42 32 kwords 150000h?157fffh sa43 32 kwords 158000h?15ffffh sa44 32 kwords 160000h?167fffh sa45 32 kwords 168000h?16ffffh sa46 32 kwords 170000h?177fffh sa47 32 kwords 178000h?17ffffh bank a sa48 32 kwords 180000h?187fffh sa49 32 kwords 188000h?18ffffh sa50 32 kwords 190000h?197fffh sa51 32 kwords 198000h?19ffffh sa52 32 kwords 1a0000h?1a7fffh sa53 32 kwords 1a8000h?1affffh sa54 32 kwords 1b0000h?1b7fffh sa55 32 kwords 1b8000h?1bffffh sa56 32 kwords 1c0000h?1c7fffh sa57 32 kwords 1c8000h?1cffffh sa58 32 kwords 1d0000h?1d7fffh sa59 32 kwords 1d8000h?1dffffh sa60 32 kwords 1e0000h?1e7fffh sa61 32 kwords 1e8000h?1effffh sa62 32 kwords 1f0000h?1f7fffh sa63 8 kwords 1f8000h?1f9fffh sa64 8 kwords 1fa000h?1fbfffh sa65 8 kwords 1fc000h?1fdfffh sa66 8 kwords 1fe000h?1fffffh ta b l e 1 0 . sector address table, s29ns016j (sheet 1 of 2) sector sector size address range bank d sa0 32 kwords 000000h?007fffh sa1 32 kwords 008000h?00ffffh sa2 32 kwords 010000h?017fffh sa3 32 kwords 018000h?01ffffh sa4 32 kwords 020000h?027fffh sa5 32 kwords 028000h?02ffffh sa6 32 kwords 030000h?037fffh sa7 32 kwords 038000h?03ffffh table 9. sector address table, s29ns032j (sheet 2 of 2) sector sector size address range
march 22, 2006 S29NS-J_00_a10 S29NS-J 33 data sheet command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 18 defines the valid register command sequences. writing incorrect ad - dress and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the rising edge of avd#. all data is latched on the rising edge of we#. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading arra y data after device po wer-up. no commands are required to retrieve data in as ynchronous mode. each bank is ready to read array data after com - pleting an embedded program or embedded erase algorithm. after the device accepts an erase suspend comma nd, the corresponding bank enters the erase- suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. bank c sa8 32 kwords 040000h?047fffh sa9 32 kwords 048000h?04ffffh sa10 32 kwords 050000h?057fffh sa11 32 kwords 058000h?05ffffh sa12 32 kwords 060000h?067fffh sa13 32 kwords 068000h?06ffffh sa14 32 kwords 070000h?077fffh sa15 32 kwords 078000h?07ffffh bank b sa16 32 kwords 080000h?087fffh sa17 32 kwords 088000h?08ffffh sa18 32 kwords 090000h?097fffh sa19 32 kwords 098000h?09ffffh sa20 32 kwords 0a0000h?0a7fffh sa21 32 kwords 0a8000h?0affffh sa22 32 kwords 0b0000h?0b7fffh sa23 32 kwords 0b8000h?0bffffh bank a sa24 32 kwords 0c0000h?0c7fffh sa25 32 kwords 0c8000h?0cffffh sa26 32 kwords 0d0000h?0d7fffh sa27 32 kwords 0d8000h?0dffffh sa28 32 kwords 0e0000h?0e7fffh sa29 32 kwords 0e8000h?0effffh sa30 32 kwords 0f0000h?0f7fffh sa31 8 kwords 0f8000h?0f9fffh sa32 8 kwords 0fa000h?0fbfffh sa33 8 kwords 0fc000h?0fdfffh sa34 8 kwords 0fe000h?0fffffh ta b l e 1 0 . s e c t o r a d d r e s s ta b l e , s 2 9 n s 0 1 6 j ( s h e e t 2 o f 2 ) sector sector size address range
34 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet the system must issue the reset command to return a ba nk to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the au - toselect mode. see the next section, reset command , for more information. see also requirements for asynchronous read operation (non-burst) and requirements for syn - chronous (burst) read operation in the device bus operations section for more information. the asynchronous read and synchronous/burst read tables provide the read parameters, and fig - ures 11 and 13 show the timings. set configuration register command sequence the configuration register command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be pro - grammed into the device is directly related to the clock frequency. the first two cycles of the command sequence are for unlock purposes. on the third cycle, the system should write c0h to the address associated with the intended wait state setting (see ta b l e 11 ). address bits a17?a12 determine the setting. note that addresses a max ?a18 are shown as ?0? but are actually don?t care. table 11. burst modes note: the burst mode is set in t he third cycle of the set wait state command sequence. upon power up, the device defaults to the maximum seven cycle wait state setting. it is recom - mended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default setting. handshaking feature the host system should set address bits a17?a12 to ?000011? for a clock frequency of 54 or 66 mhz, assuming continuous burst is desired in both cases, for op timal burst operation. ta b l e 12 describes the typical number of clock cycles (wait states) for various conditions. burst mode third cycle addresses for wait states wait states 0 1 2 3 4 5 clock cycles 2 3 4 5 6 7 continuous 00555h 01555h 02555h 03555h 04555h 05555h 8-word linear (wrap around) 08555h 09555h 0a555h 0b555h 0c555h 0d555h 16-word linear (wrap around) 10555h 11555h 12555h 13555h 14555h 15555h 32-word linear (wrap around) 18555h 19555h 1a555h 1b555h 1c555h 1d555h 8-word linear (no wrap around) 28555h 29555h 2a555h 2b555h 2c555h 2d555h 16-word linear (no wrap around) 30555h 31555h 32555h 33555h 34555h 35555h 32-word linear (no wrap around) 38555h 39555h 3a555h 3b555h 3c555h 3d555h
march 22, 2006 S29NS-J_00_a10 S29NS-J 35 data sheet ta b l e 1 2 . wait states for handshaking note: in the 8-, 16- and 32-word burst read modes, the address po inter does not cross 64-word bo undaries when wrap around is enabled (at address 3fh, and at addres ses offset from 3fh by multiples of 64). the autoselect function allows the host system to determine whether the flash device is enabled for handshaking. see the ?autoselect command sequence? section for more information. sector lock/unlock command sequence the sector lock/unlock command sequence allows the system to determine which sectors are pro - tected from accidental writes. when the device is first powered up, all sectors are locked. to unlock a sector, the system must write the sector lock/unlock command sequence. two cycles are first written: addresses are don?t care and data is 60h. during the third cycle, the sector address (sla) and unlock command (60h) is written, while sp ecifying with address a6 whether that sector should be locked (a6 = v il ) or unlocked (a6 = v ih ). after the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing f0h (reset command). note that the last two outermost boot sectors can be locked by taking the wp# signal to v il . also, if a cc is at v il all sectors are locked; if the a cc input is at v id , all sectors are unlocked. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between th e sequence cycles in a program command se - quence before programming begins. this resets th e bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that ba nk to the erase-suspend-read mode. once pro - gramming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command se - quence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase op eration, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). conditions at address typical no. of clock cycles after avd# low 40 mhz 54/66 mhz initial address is even 4 5 initial address is odd 5 6 initial address is even, and is at boundary crossing ( note ) 6 7 initial address is odd, and is at boundary crossing* 7 8
36 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. ta b l e 18 shows the address and data requirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be writ - ten while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the autoselect command. the bank then enters the autoselect mode. the system may read at any address within the same bank any num - ber of times without initiating another autoselect command sequence. the following table describes the address requirements for the various autoselect functions, and the resulting data. ba represents the bank address, and sa represent the sector address. the device id is read in three cycles. ta b l e 1 3 . autoselect device id the system must write the reset command to retu rn to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writ - ing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally gen - erated program pulses and verifies the programmed cell margin. ta b l e 18 shows the address and data requirements for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program oper - ation by monitoring dq7 or dq6/dq2. refer to the write operation status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. description address read data s29ns128j s29ns064j s29ns032j s29ns016j manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 007eh 277eh 2a7eh 297eh device id, word 2 (ba) + 0eh 0016h 2702h 2a24h 2915h device id, word 3 (ba) + 0fh 0000h 2700h 2a00h 2900h sector block lock/unlock (sa) + 02h 0001h (locked), 0000h (unlocked) revision id (ba) + 03h tbd, based on nokia spec
march 22, 2006 S29NS-J_00_a10 S29NS-J 37 data sheet programming is allowed in any sequence and across sector boundaries. a bit cannot be pro - grammed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bit to indicate the operation was successful. however, a suc - ceeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? note: by default, upon every power up, the sectors will automatically be locked. therefore, everytime after power-up, users need to write unlock command to unlock the sectors before giving program/erase command. unlock bypass command sequence the unlock bypass feature allows the system to program to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program com - mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program ad - dress and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. ta b l e 18 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset com - mands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the a cc input. when the system asserts a cc on this input, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher volt - age on the a cc input to accelerate the operation. figure 1 illustrates the algorithm for the program operation. refer to the erase/program opera - tions table in the ac characteristics section for parameters, and figure 15 for timing diagrams.
38 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet figure 1. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in tu rn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these oper - ations. ta b l e 18 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and ad - dresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to the write operation status section for information on these sta - tus bits. any commands written during the chip erase op eration are ignored. however, note that a hard - ware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 2 illustrates the algorithm for the erase operation. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams. start write program command sequence data poll from system verify data? no ye s last address? no ye s programming completed increment address embedded program algorithm in progress write unlock cycles: address xxx, data 60 address xxx, data 60 address sla, data 60 note: see table 18 for program command sequence.
march 22, 2006 S29NS-J_00_a10 S29NS-J 39 data sheet sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writ - ing two unlock cycles, followed by a set-up comma nd. two additional unlock cycles are written, and are then followed by the address of the sect or to be erased, and the sector erase command. ta b l e 18 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algo - rithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea (sector erase accept) occurs. during the time-out period, addi tional sector addresses and sector erase com - mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than t sea , otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out pe riod resets that bank to the read mode. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and ad - dresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7 or dq6/ dq2 in the erasing bank. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 2 illustrates the algorithm for the erase operation. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams. accelerated sector group erase under certain conditions, the device can erase sectors in parallel. this method of erasing sectors is faster than the standard sector erase command sequence. ta b l e 14 lists the sector erase groups. the accelerated sector group er ase function must not be used more than 100 times per sector. in addition, accelerated sect or group erase should be performed at room temperature (30 +/- 10 c).
40 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ta b l e 1 4 . accelerated sector erase groups, s29ns128j ta b l e 1 5 . accelerated sector erase groups, s29ns064j sa0?sa7 sa128?sa135 sa8?sa15 sa136?sa143 sa16?sa23 sa144?sa151 sa24?sa31 sa152?sa159 sa32?sa39 sa160?sa167 sa40?sa47 sa168?sa175 sa48?sa55 sa176?sa183 sa56?sa63 sa184?sa191 sa64?sa71 sa192?sa199 sa72?sa79 sa200?sa207 sa80?sa87 sa208?sa215 sa88?sa95 sa216?sa223 sa96?sa103 sa224?sa231 sa104?sa111 sa232?sa239 sa112?sa119 sa240?sa247 sa120?sa127 sa248?sa254 sa0?sa7 sa8?sa15 sa16?sa23 sa24?sa31 sa32?sa39 sa40?sa47 sa48?sa55 sa56?sa63 sa64?sa71 sa72?sa79 sa80?sa87 sa88?sa95 sa96?sa103 sa104?sa111 sa112?sa119 sa120?sa126
march 22, 2006 S29NS-J_00_a10 S29NS-J 41 data sheet ta b l e 1 6 . accelerated sector erase groups, s29ns032j ta b l e 1 7 . accelerated sector erase groups, s29ns016j use the following procedure to perform accelerated sector group erase: 1. unlock all sectors in a sector group to be erased using the sector lock/unlock command se- quence. all sectors that remain locked will not be erased. 2. apply 12 v to the a cc input. this voltage must be applied at least 1 s before executing step 3 . 3. write 80h to any address within a sector group to be erased. 4. write 10h to any address within a sector group to be erased. 5. monitor status bits dq2/dq6 or dq7 to determ ine when erasure is complete, just as in the standard erase operation. see write operation status for further details. 6. lower a cc from 12 v to v cc . 7. relock sectors as required. sa0?sa3 sa16-sa19 sa32-sa35 sa48-sa51 sa4?sa7 sa20-sa23 sa36-sa39 sa52-sa55 sa8?sa11 sa24-sa27 sa40-sa43 sa56?sa59 sa12-sa15 sa28-sa31 sa44-sa47 sa60?sa62 sa0?sa1 sa8-sa9 sa16-sa17 sa24-sa25 sa2?sa3 sa10-sa11 sa18-sa19 sa26-sa27 sa4?sa5 sa12-sa13 sa20-sa21 sa28-sa29 sa6?sa7 sa14-sa15 sa24-sa25 sa30
42 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, program data to, any sector not selected for erasure. the system may also lock or unlock any sector while the erase operation is suspended. the system must not write the sector lock/unlock command to sectors select ed for erasure. the bank address is re - quired when writing this command. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded pro - gram algorithm. when the erase suspend command is written during the sector erase operation, the device re - quires t esl (erase suspend latency) to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the de - vice ?erase suspends? all sectors selected for erasure.) the system may also lock or unlock any sector while in the erase-suspend-read mode. reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write op - eration status section for information on these status bits. after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend- read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect functions and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is requ ired when writing this command. further writes of the resume command are ignored. another er ase suspend command can be written after the chip has resumed erasing.
march 22, 2006 S29NS-J_00_a10 S29NS-J 43 data sheet figure 2. erase operation s tart write er as e comm a nd s e qu ence d a t a poll from s y s tem d a t a = ffh? no ye s er asu re completed em b edded er as e a lgorithm in progre ss notes: 1. see table 18 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
44 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ta b l e 1 8 . command definitions command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read ( 7 ) 1ra rd reset ( 8 ) 1 xxx f0 autoselect ( 9 ) manufacturer id 4 555 aa 2aa 55 (ba)555 90 (ba)x00 0001 device id 6 555 aa 2aa 55 (ba)555 90 (ba)x01 ( 10 )(ba)x0e( 11 )(ba) x0f ( 12 ) sector lock verify ( 13 ) 4 555 aa 2aa 55 (sa)555 90 (sa)x02 ( 13 ) revision id ( 14 ) 4 555 aa 2aa 55 (ba)555 90 (ba)x03 ( 14 ) unlock bypass mode entry 3 555 aa 2aa 55 555 20 program ( 15 ) 2 xxx a0 pa pd reset ( 16 ) 2ba 90xxx00 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend ( 17 ) 1ba b0 erase resume ( 18 ) 1ba 30 sector lock/unlock 3 xxx 60 xxx 60 sla 60 set config. register ( 19 ) 3 555 aa 2aa 55 (cr)555 c0 cfi query ( 20 ) 155 98 legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory locati on to be programmed. addresses latch on the falling edge of the we # or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a13 uniquely select any sector. ba = address of the bank (a 22?a21 for s29ns128j, a21?a20 for s29ns064j, a20?a19 for s29ns032j, a19?a18 for s29ns016j) that is being switched to au toselect mode, is in bypass mode, or is being erased. sla = address of the sector to be locked. set sector address (sa) and either a6 = 1 for unlocked or a6 = 0 for locked. cr = configuration register set by address bits a17?a12. notes: 1. see table 1 for description of bus operations. 2 . all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4 . data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a max ?a12 are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when ba nk is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is pr oviding status information). 9. the fourth cycle of the autoselect command sequence is a read cycle. the system must read device ids across the 4th, 5th, and 6th cycles, the system must provide the bank address. see the autoselect command sequence section for more information. 10. for s29ns128j, the data is 007e h. for s29ns064j, the data is 277eh. for s29ns032j, the data is 2a7eh. for s29ns016j, the data is 297eh. 11. for s29ns128j, the data is 0016h . for s29ns064j, the data is 2702h, for s29ns032j, the data is 2a24h, for s29ns016j, the data is 2915h. 12. for s29ns128j, the data is 0000h , for s29ns064j, the data is 2700h, for s29ns032j, the data is 2a00h for s29ns016j, the data is 2900h. 13. the data is 0000h for an unlocked sector and 0001h for a locked sector. 14. the data is tbd, based on nokia spec. 15. the unlock bypass command sequen ce is required prior to this command sequence. 16. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 17. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 18. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 19. the addresses in the third cycl e must contain, on a17?a12, the additional wait counts to be set. see ?set configuration register command sequence? . 20. command is valid when device is ready to read array data or when device is in autoselect mode.
march 22, 2006 S29NS-J_00_a10 S29NS-J 45 data sheet write operation status the device provides several bits to determine th e status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 20 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whet her a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the de vice outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program addr ess to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi - mately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# po lling produces a ?0? on dq7. when the embed - ded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp (all sectors protected toggle time), then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase al - gorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asyn - chronously with dq6?dq0 while output enable (o e#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6?dq0 may be still invalid. valid data on dq7?dq0 will appear on successive read cycles. ta b l e 20 shows the outputs for data# polling on dq 7. 3 shows the data# polling algorithm. 18 in the ac characteristics section shows the data# polling timing diagram.
46 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet figure 3. data# polling algorithm dq7 = d a t a ? ye s no no dq5 = 1? no ye s ye s fail pa ss re a d dq7?dq0 addr = va re a d dq7?dq0 addr = va dq7 = d a t a ? s tart notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
march 22, 2006 S29NS-J_00_a10 S29NS-J 47 data sheet rdy: ready the rdy pin is a dedicated status output that in dicates valid output data on a/dq15?a/dq0 dur - ing burst (synchronous) reads. when rdy is asserted (rdy = v oh ), the output data is valid and can be read. when rdy is de-asserted (rdy = v ol ), the system should wait until rdy is re-as - serted before expecting the next word of data. in synchronous (burst) mode with ce# = oe# = v il , rdy is de-asserted under the following con - ditions: during the initial access; after crossing the internal boundary between addresses 3eh and 3fh (and addresses offset from these by a multiple of 64); and when the clock frequency is less than 6 mhz (in which case rdy is de-asserted every third clock cycle). the rdy pin will also switch during status reads when a clock signal drives the clk input. in addition, rdy = v oh when ce# = v il and oe# = v ih , and rdy is hi-z when ce# = v ih . in asynchronous (non-burst) mode, the rdy pin does not indicate valid or invalid output data. instead, rdy = v oh when ce# = v il , and rdy is hi-z when ce# = v ih . dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time- out. during an embedded program or erase algorith m operation, successive read cycles to any ad - dress cause dq6 to toggle. note that oe# must be low during toggle bit status reads. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately t asp , then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se - lected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog - gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately after t psp the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed - ded program algorithm is complete. see the following for additional information: (toggle bit flowchart), dq6: toggle bit i (descrip - tion), 19 (toggle bit timing diagram), and ta b l e 19 (compares dq2 and dq6). dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. note that oe# must be low during to ggle bit status reads. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates
48 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sec - tors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 20 to compare outputs for dq2 and dq6. see the following for additional information: (toggle bit flowchart), dq6: toggle bit i (descrip - tion), 19 (toggle bit timing diagram), and ta b l e 19 (compares dq2 and dq6). s tart no ye s ye s dq5 = 1? no ye s dq6 = toggle? no re a d byte (dq0-dq7) addre ss = va dq6 = toggle? re a d byte twice (dq 0-dq7) adrde ss = va re a d byte (dq0-dq7) addre ss = va fail pa ss note: the system should recheck th e toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsection s on dq6 and dq2 for more information. figure 4. toggle bit algorithm
march 22, 2006 S29NS-J_00_a10 S29NS-J 49 data sheet ta b l e 1 9 . dq6 and dq2 indications reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would com - pare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the sy stem can read array da ta on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still tog - gling, the system also should note whether the va lue of dq5 is high (see the section on dq5). if it is, the system should then determine again whet her the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went hi gh. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through suc - cessive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
50 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase time r does not apply to the chip erase command.) if additional sectors are selected for erasure, the en tire time-out also applie s after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the syst em should read the status of dq7 (data# poll - ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 20 shows the status of dq3 relative to the other status bits. ta b l e 2 0 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embe dded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system mu st always provide the bank address where the embedded algorithm is in progress. the device outputs arra y data if the system addresses a non-busy bank. 4. the system may read either asynchronously or synchron ously (burst) while in erase suspend. rdy will function ex - actly as in non-erase-suspended mode. status dq7 ( note 2 ) dq6 dq5 ( note 1 ) dq3 dq2 ( note 2 ) standard mode embedded program algorithm dq7# to gg l e 0 n/a no toggle embedded erase algorithm 0 to gg l e 0 1 to g gl e erase suspend mode erase suspend read ( note 4 ) erase suspended sector 1 no toggle 0 n/a to g gl e non-erase suspended sector data data data data data erase suspend program dq7# to gg l e 0 n/a n/a
march 22, 2006 S29NS-J_00_a10 S29NS-J 51 data sheet absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground, all inputs and i/os except a cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc + 0.5 v v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v a cc (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v output short circuit current (note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. duri ng voltage transitions, input at i/os may undershoot v ss to ? 2.0 v for periods of up to 20 ns during voltage transitions inputs might overshooot to v cc +0.5 v for periods up to 20 ns. see figure 5 . maximum dc voltage on output and i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 6 . 2. minimum dc input voltage on a cc is ?0.5 v. during voltage transitions, a cc may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 5 . maximum dc input voltage on a cc is +12.5 v which may overshoot to +13.5 v for periods up to 20 ns. 3. no more than one output may be shor ted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. this is a stress rating only; function al operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. expo sure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c v cc supply voltages v cc min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.7 v v cc max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.95 v note: operating ranges define those limits between whic h the functionality of the device is guaranteed. figure 5. maximum negative overshoot waveform figure 6. maximum positive overshoot waveform 20 ns 20 ns +0.9 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v 20 ns 2.0 v
52 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet dc characteristics cmos compatible notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 60 ns. typical sleep mode current is equal to i cc3 . 5. specifications assume 8 i/os switching and continuous burst length. 6. not 100% tested. a cc is not a power supply pin. parameter description test conditions ( note 1 ) min ty p max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ( note 5 ) ce# = v il , oe# = v il 25 30 ma i cc1 v cc active asynchronous read current ( note 2 ) ce# = v il , oe# = v ih 5 mhz 12 16 ma 1 mhz 3.5 5 ma i cc2 v cc active write current ( note 3 ) ce# = v il , oe# = v ih , a cc = v ih 15 40 ma i cc3 v cc standby current ( note 4 ) ce# = v ih , reset# = v ih 9 40 a i cc4 v cc reset current reset# = v il, clk = v il 9 40 a i cc5 v cc active current (read while write) ce# = v il , oe# = v il 40 60 ma i ppw accelerated program current ( note 6 ) a cc = 12 v 7 15 ma i ccw 5 10 i ppe accelerated erase current ( note 6 ) a cc = 12 v 7 15 ma i cce 5 10 v il input low voltage ?0.5 0.4 v v ih input high voltage v cc ? 0.4 v cc + 0.2 v v ol output low voltage i ol = 100 a, v cc = v cc min 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min v cc ? 0.1 v v id voltage for accelerated program 11.5 12.5 v v lko low v cc lock-out voltage 1.0 1.4 v
march 22, 2006 S29NS-J_00_a10 S29NS-J 53 data sheet test conditions ta b l e 2 1 . test specifications key to switching waveforms switching waveforms test condition all speeds unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v cc v input timing measurem ent reference levels v cc /2 v output timing measur ement reference levels v cc /2 v c l device under tes t figure 7. test setup waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v o u tp u t me asu rement level inp u t v cc /2 v cc /2 figure 8. input waveforms and measurement levels
54 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics v cc power-up figure 9. v cc power-up diagram parameter description te s t s e t u p speed unit t vcs v cc setup time min 50 s t rsth reset# low hold time min 50 s v cc re s et# t vc s t r s th
march 22, 2006 S29NS-J_00_a10 S29NS-J 55 data sheet ac characteristics clk characterization figure 10. clk characterization parameter description 0p (66 mhz) 0l (54 mhz) unit f clk clk frequency max 66 54 mhz t clk clk period min 15 18.5 ns t ch clk high time min 3.5 4.5 ns t cl clk low time t cr clk rise time max 3 3 ns t cf clk fall time t clk t cl t ch t cr t cf clk
56 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics synchronous/burst read note: not 100% tested notes: 1. figure shows total number of clock set to five. 2. if any burst address occurs at a 64-word boundary, two ad ditional clock cycles are inserted and are indicated by rdy. figure 11. burst mode read (66 and 54 mhz) parameter description 0p (66 mhz) 0l (54 mhz) unit jedec standard t iacc initial access time max 71 87.5 ns t bacc burst access time valid clock to output delay max 11 13.5 ns t avds avd# setup time to clk min 4 5 ns t avdh avd# hold time from clk min 6 7 ns t avdo avd# high to oe# low min 0 ns t acs address setup time to clk min 4 5 ns t ach address hold time from clk min 6 7 ns t bdh data hold time from next clock cycle (note) min 3 ns t oe output enable to data, ps, or rdy valid max 11 13.5 ns t cez chip enable to high z max 10 ns t oez output enable to high z max 10 ns t ces ce# setup time to clk min 4 5 ns t rdys rdy setup time to clk min 4 5 ns t racc ready access time from clk max 11 13.5 ns da da + 1 da + 2 da + n oe# a/dq15 ? a/dq0 a max ? a16 aa avd# rdy clk ce# t ces t acs t avds t avdh t avdo t ach t bacc t racc t oe t oez t cez t iacc t ryds t bdh aa 5 cycles for initial access shown. programmable wait state function is set to 03h. 15.2 ns typ. (66 mhz) 18.5 ns typ. (54 mhz) hi-z hi-z hi-z
march 22, 2006 S29NS-J_00_a10 S29NS-J 57 data sheet ac characteristics notes: 1. figure shows total number of clock cycles set to four. 2. if any burst address occurs at a 64-word boundary, two ad ditional clock cycle are inserted, and are indicated by rdy. figure 12. burst mode read (40 mhz) da da + 1 da + 2 da + n oe# a/dq15 ? a/dq0 a max ? a16 aa avd# rdy clk ce# t ces t acs t avds t avdh t avdo t ach t bacc t oe t oez t cez t iacc t bdh aa 4 cycles for initial access shown. programmable wait state function is set to 02h. 25 ns typ. t racc hi-z hi-z hi-z t ryds
58 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics asynchronous read note: not 100% tested . note: ra = read address, rd = read data . figure 13. asynchronous mode read parameter description 0p (66 mhz) 0l (54 mhz) unit jedec standard t ce access time from ce# low max 65 70 ns t acc asynchronous access time max 65 70 ns t avdp avd# low time min 11 12 ns t aavds address setup time to rising edge of avd min 4 5 ns t aavdh address hold time from rising edge of avd min 3.7 3.7 ns t oe output enable to output valid max 11 13.5 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t ce we# a m a x ? a16 ce# oe# v a lid rd t acc t oeh t oe a/dq15 ? a/dq0 t oez t aavdh t avdp t aavd s avd# ra ra
march 22, 2006 S29NS-J_00_a10 S29NS-J 59 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t readyw reset# pin low (durin g embedded algorithms) to read mode ( see note ) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode ( see note ) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read ( see note ) min 200 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 14. reset timings
60 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programmi ng performance? section for more information. 3. does not include the preprogramming time. parameter description 0p (66 mhz) 0l (54 mhz) unit jedec standard t avav t wc write cycle time ( note 1 ) min 45 80 ns t avwl t as address setup time min 4 5 ns t wlax t ah address hold time min 6 7 ns t avdp avd# low time min 11 12 ns t dvwh t ds data setup time min 25 45 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write typ 0 ns t elwl t cs ce# setup time typ 0 ns t wheh t ch ce# hold time typ 0 ns t wlwh t wp /t wrl write pulse width typ 25 50 ns t whwl t wph write pulse width high typ 20 30 ns t sr/w latency between read and write operations min 0 ns t acc a cc rise and fall time min 500 ns t vps a cc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t sea sector erase accept time-out max 50 s t esl erase suspend latency max 35 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a prot typ 1 s
march 22, 2006 S29NS-J_00_a10 S29NS-J 61 data sheet ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a max ?a16 are don?t care during command sequence unlock cycles. figure 15. program operation timings oe# ce# a/dq15 ? a/dq0 a max ? a16 avd# we# clk v cc 555h a0h pd t as t wp t ah t wc t wph pa pa t vcs t cs t dh t ch in progress t whwh1 va va complete va va program command sequence (last two cycles) read status data t ds v ih v il t avdp
62 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics notes: 1. sa is the sector addr ess for sector erase. 2. address bits a max ?a16 are don?t cares during unlock cycles in the command sequence. figure 16. chip/sector erase operations oe# ce# a/dq15 ? a/dq0 a max ? a16 avd# we# clk v cc 2aah 55h 30h t as t wp t ah t wc t wph sa sa t vcs t cs t dh t ch in progress t whwh2 va va complete va va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp
march 22, 2006 S29NS-J_00_a10 S29NS-J 63 data sheet ac characteristics notes: 1. a cc can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operation. figure 17. accelerated unlock bypass programming timing ce# avd# we# a max ? a16 a/dq15 ? a/dq0 ce# v pp don't care don't care a0h pa pa pd v id v il or v ih t vpp t vps
64 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics notes: 1. all status reads are asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. figure 18. data# polling timings (during embedded algorithm) notes: 1. all status reads are asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. figure 19. toggle bit timings (during embedded algorithm) we# ce# oe# high z t oe high z a max ? a16 a/dq15 ? a/dq0 avd# t oeh t ce t ch t oez t cez status data status data t acc va va va va we# ce# oe# high z t oe high z a max ? a16 a/dq15 ? a/dq0 avd# t oeh t ce t ch t oez t cez status data status data t acc va va va va
march 22, 2006 S29NS-J_00_a10 S29NS-J 65 data sheet ac characteristics note: 8-word linear burst mode shown. 16- an d 32-word linear burst read modes behave similarly. d0 represents the first word of the linear burst. figure 20. 8-, 16-, and 32-word linear burst address wrap around note: cxx indicates the clock that triggers data dxx on the outputs; for exam ple, c60 triggers d60. figure 21. latency with boundary crossing clk addre ss (hex) d0 d1 d2 a/dq15 ? a/dq0 ce# addre ss wr a p s ba ck to b eginning of a ddre ss gro u p. 39 39 3a 3b 3c 3d 3e 3f 38 initi a l acce ss v il v ih avd# v il v ih d3 d4 d5 d6 d7 ( s t a y s low) v il oe# clk address (hex) c60 c61 c62 c63 c63 c63 c64 c65 c66 c67 d60 d61 d62 d63 d64 d65 d66 d67 (stays high) avd# rdy a/dq15 ? a/dq0 oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003fh: 00007fh, 0000bfh, etc. address 000000h is also a boundary crossing. 3c 3d 3e 3f 40 41 42 43 latency t racc v ih v il v ih v il
66 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet ac characteristics note: devices should be programmed with wait states as discussed in the ?programmable wait stat e? section on page 16. figure 22. initial access at 3eh with address boundary latency note: if t avdsm > 1 clk cycle, wait state usage is reduced. figure show s 40 mhz clock, handshaking enabled. wait state usage is 4 clock cycles instead of 5. note that t avdsm must be less than 76 s for burst operation to begin . figure 23. example of extended valid address reducing wait state usage clk avd# rdy address high-z a/dq15 ? a/dq0 oe# d0 d1 d2 device is programmable from 2 to 7 total cycles during initial access (here, programmable wait state function is set to 04h; 6 cycles total) 2 additional wait states if address is at boundary avd# low with clock present enables burst read mode address a max ? a16 t oe clk avd# rdy hi-z a/dq oe# ce# d0 d1 d2 t iacc t avdsm addresses
march 22, 2006 S29NS-J_00_a10 S29NS-J 67 data sheet ac characteristics note: breakpoints in waveforms indicate that system may alternatel y read array data from the ?non -busy bank? while checking the status of the program or erase operation in the ?busy? bank. th e system should read status tw ice to ensure valid information . figure 24. back-to-back read/write cycle timings oe# ce# we# t oeh a/dq15 ? a/dq0 a m a x ? a16 avd# pd/30h pa / s a aah 555h ra pa / s a t wc t d s t dh t rc t rc t oe t a s t ah t acc t oeh t wp t ghwl t oez t wc t s r/w l as t cycle in progr a m or s ector er as e comm a nd s e qu ence re a d s t a t us ( a t le as t two cycle s ) in sa me ba nk a nd/or a rr a y d a t a from other ba nk begin a nother write or progr a m comm a nd s e qu ence rd ra ra ra rd t wph
68 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet erase and programming performance notes: 1. typical program and erase times as sume the following conditions: 25 c, 1.8 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 18 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles. bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter ty p ( note 1 ) max ( note 2 ) unit comments sector erase time 32 kword 0.4 5 s excludes 00h programming prior to erasure ( note 4 ) 8 kword 0.2 5 chip erase time 128 mb 108 s 64 mb 54 32 mb 27 16 mb 13.5 word programming time 9 210 s excludes system level overhead ( note 5 ) accelerated word programming time 4 120 s chip programming time ( note 3 ) 128 mb 96 288 s excludes system level overhead ( note 5 ) 64 mb 48 144 32 mb 24 72 16 mb 12 36 accelerated chip programming time 128 mb 32 96 s 64 mb 16 48 32 mb 8 24 16 mb 4 12 accelerated chip erase time 128 mb 50 s 64 mb 25 32 mb 12.5 16 mb 6.25 parameter symbol parameter description te s t s e t u p ty p max unit c in input capacitance v in = 0 4.2 5.0 pf c out output capacitance v out = 0 5.4 6.5 pf c in2 control pin capacitance v in = 0 3.9 4.7 pf
march 22, 2006 S29NS-J_00_a10 S29NS-J 69 data sheet physical dimensions s29ns128j vdc048?48-ball very thin fine-pitch ball grid array (fbga) 10 x 11 mm package note: for reference only. bsc is an ansi standard for basic space centering. package vdc 048 jedec n/a 9.95 mm x 10.95 mm nom package s ymbol min nom max note a 0.86 --- 1.00 overall thickne ss a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickne ss d 9.85 9.95 10.05 body s ize e 10.85 10.95 11.05 body s ize d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix s ize d direction me 4 row matrix s ize e direction n 48 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 ball pitch s d / s e 0.25 s older ball placement 3241 \ 16-038.9h. aa 01 note s : 1. dimen s ioning and tolerancing per a s me y14.5m-1994. 2. all dimen s ion s are in millimeter s . 3. ball po s ition de s ignation per je s d 95-1, s pp-010 (except a s noted). 4. e repre s ent s the s older ball grid pitch. 5. s ymbol "md" i s the ball row matrix s ize in the "d" direction. s ymbol "me" i s the ball column matrix s ize in the "e" direction. n i s the total number of s older ball s . 6 dimen s ion " b " i s mea s ured at the maximum ball diameter in a plane parallel to datum c. 7 s d and s e are mea s ured with re s pect to datum s a and b and define the po s ition of the center s older ball in the outer row. when there i s an odd number of s older ball s in the outer row parallel to the d or e dimen s ion, re s pectively, s d or s e = 0.000. when there i s an even number of s older ball s in the outer row, s d or s e = e/2 8. not u s ed. 9. "+" indicate s the theoretical center of depopulated ball s . 10 a1 corner to be identified by chamfer, la s er or ink mark, metallized mark indentation or other mean s . index mark a1 corner nf4 nf1 nf8 1 2 43 5 6 8 97 nf2 nf3 a b nf7 nf5 c d 10 nf6 d a 10 e a1 corner s e 7 e1 d1 e 1.00 1.00 7 s d b 6 b c m c m 0.05 0.15 a 1.00 1.00 c 0.10 c 0.08 a b c a2 s eating plane a1
70 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet s29ns064j vdd044?44-ball very thin fine-pitch ball grid array (fbga) 9.2 x 8 mm package note: for reference only. bsc is an ansi standard for basic space centering. package vdd 044 jedec n/a 8.00 mm x 9.20 mm nom package s ymbol min nom max note a 0.86 --- 1.00 overall thickne ss a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickne ss d 7.90 8.00 8.10 body s ize e 9.10 9.20 9.30 body s ize d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix s ize d direction me 4 row matrix s ize e direction n 44 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 ball pitch s d / s e 0.25 s older ball placement 3239 \ 16-03 8 note s : 1. dimen s ioning and tolerancing per a s me y14.5m-19 9 2. all dimen s ion s are in millimeter s . 3. ball po s ition de s ignation per je s d 95-1, s pp-010 (e x a s noted). 4. e repre s ent s the s older ball grid pitch. 5. s ymbol "md" i s the ball row matrix s ize in the "d" direction. s ymbol "me" i s the ball column matrix s ize in the "e" direction. n i s the total number of s older ball s . 6 dimen s ion " b " i s mea s ured at the maximum ball diameter in a plane parallel to datum c. 7 s d and s e are mea s ured with re s pect to datum s a and b and define the po s ition of the center s older ball in the outer row. when there i s an odd number of s older ball s in the outer row parallel to the d or e dimen s ion, re s pectively, s d or s e = 0.000. when there i s an even number of s older ball s in the outer row, s d or s e = e/2 8. not u s ed. 9. "+" indicate s the theoretical center of depopula t ball s . 10 a1 corner to be identified by chamfer, la s er or i n mark, metallized mark indentation or other mea n index mark a1 corner s ide view top view bottom view nf1 nf3 2 1 3 4 5 6 987 10 a nf2 c d nf4 b d a 10 d1 s d b s e 1.00 e a2 a1 e s eating plane a m m c c 0.15 0.05 b a1 co 7 7 6 c 0.10 c b a c 0.08 1.00
march 22, 2006 S29NS-J_00_a10 S29NS-J 71 data sheet s29ns032j and s29ns016j vde044?44-ball very thin fine -pitch ball grid array (fbga) 7.7 x 6.2 mm package note: for reference only. bsc is an ansi standard for basic space centering. package vde 044 jedec n/a 7.70 mm x 6.20 mm nom package s ymbol min nom max note a 0.86 --- 1.00 overall thickne ss a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickne ss d 7.65 7.7 7.75 body s ize e 6.15 6.2 6.25 body s ize d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix s ize d direction me 4 row matrix s ize e direction n 44 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 b s c. ball pitch s d / s e 0.25 b s c. s older ball placement depopulated s older ball s 3308.1 \ 16-038.9l note s : 1. dimen s ioning and tolerancing per a s me y14.5m-1994. 2. all dimen s ion s are in millimeter s . 3. ball po s ition de s ignation per je s d 95-1, s pp-010 (except a s noted). 4. e repre s ent s the s older ball grid pitch. 5. s ymbol "md" i s the ball row matrix s ize in the "d" direction. s ymbol "me" i s the ball column matrix s ize in the "e" direction. n i s the total number of s older ball s . 6 dimen s ion " b " i s mea s ured at the maximum ball diameter in a plane parallel to datum c. 7 s d and s e are mea s ured with re s pect to datum s a and b and define the po s ition of the center s older ball in the outer row. when there i s an odd number of s older ball s in the outer row parallel to the d or e dimen s ion, re s pectively, s d or s e = 0.000. when there i s an even number of s older ball s in the outer row, s d or s e = e/2 8. not u s ed. 9. "+" indicate s the theoretical center of depopulated ball s . 10 a1 corner to be identified by chamfer, la s er or ink mark, metallized mark indentation or other mean s . index mark a1 corner s ide view top view d a 10 a2 a1 e s eating plane c 0.10 c b a c 0.08 bottom view nf1 nf3 2 1 3 4 5 6 987 10 a nf2 c d nf4 b d1 s d b e1 s e 1.00 e a m m c c 0.05 0.15 b a1 corner 7 7 6 1.00
72 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet appendix a: daisy chain information table 22. daisy chain part for 128mbit 110 nm flash products (vdc048, 10 x 11 mm) ta b l e 2 3 . vdc048 package information ta b l e 2 4 . vdc048 connections daisy chain part number package marking daisy chain connection spansion 128mb flash part number flash description lead (pb) - free compliant: am29n128hvcd21ct lead (pb) - free: am29n128hvcd21cft n128hd21c n128hd21cf die level s29ns128j 128mbit 110nm component type/name vdc048 solder resist opening 0.25 + 0.05 mm daisy chain connection level on die lead-free compliant yes quantity per reel 550 (300 units per reel by special request to factory) c1?d1 c6?d6 a10?b10 a5?b5 c2?d2 c7?d7 a9?b9 a4?b4 c3?d3 c8?d8 a8?b8 a3?b3 c4?d4 c9?d9 a7?b7 a2?b2 c5?d5 c10?d10 a6?b6 a1?b1 on substrate nf1?nf4 nf2?nf5 nf16-nf19 nf17-nf20
march 22, 2006 S29NS-J_00_a10 S29NS-J 73 data sheet figure 25. vdc048 daisy chain layout (top view, balls facing down) 1 2 3 4 5 6 7 8 9 10 a b c d nf16 nf17 nf4 nf5 nf2 nf20 nf1 nf19
74 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet appendix b: daisy chain information ta b l e 2 5 . daisy chain part for 64mbit 110 nm flash products (vdd044, 9.2 x 8 mm) ta b l e 2 6 . vdd044 package information ta b l e 2 7 . vdd044 connections daisy chain part number package marking daisy chain connection spansion 64mb flash part number description lead (pb) - free compliant: am29n643gvad21ct lead (pb)- free: am29n643gvad21cft n643gd21c n643gd21cf die level s29ns064j 64mbit 110nm component type/name vdd044 solder resist opening 0.25 + 0.05 mm daisy chain connection level on die lead-free compliant yes quantity per reel 600 (300 units per reel by special request to factory) c1?d1 c6?d6 a10?b10 a5?b5 c2?d2 c7?d7 a9?b9 a4?b4 c3?d3 c8?d8 a8?b8 a3?b3 c4?d4 c9?d9 a7?b7 a2?b2 c5?d5 c10?d10 a6?b6 a1?b1 on substrate nf1?nf3 nf2?nf4
march 22, 2006 S29NS-J_00_a10 S29NS-J 75 data sheet figure 26. vdd044 daisy chain layout (top view, balls facing down) 1 2 3 4 5 6 7 8 9 10 a b c d nf3 nf4 nf1 nf2
76 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet appendix c: daisy chain information ta b l e 2 8 . daisy chain part for 32 and 16 mbit 110 nm flash products (vde044, 7.7 x 6.2 mm) ta b l e 2 9 . vde044 package information ta b l e 3 0 . vde044 connections daisy chain part number package marking daisy chain connection spansion 64mb flash part number description lead (pb) - free compliant: s99dcvde044sda002 lead (pb)- free: s99dcvde044sdf002 99dcvde044sda00 99dcvde044sdf00 die level s29ns032j s29ns016j 64mbit 110nm 32mbit 110nm component type/name vde044 solder resist opening 0.25 + 0.05 mm daisy chain connection level on die lead-free compliant yes quantity per 7-inch reel 600 (300 units per reel by special request to factory) c1?d1 c6?d6 a10?b10 a5?b5 c2?d2 c7?d7 a9?b9 a4?b4 c3?d3 c8?d8 a8?b8 a3?b3 c4?d4 c9?d9 a7?b7 a2?b2 c5?d5 c10?d10 a6?b6 a1?b1 on substrate nf1?nf3 nf2?nf4
march 22, 2006 S29NS-J_00_a10 S29NS-J 77 data sheet figure 27. vde044 daisy chain layout (top view, balls facing down) 1 2 3 4 5 6 7 8 9 10 a b c d nf3 nf4 nf1 nf2
78 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet revision summary revision a (may 16, 2003) initial release. revision a1 (august 11, 2003) connection diagram modified connection diagrams for am29n129j and s29ns064j. input/output descriptions changed v ss to gnd, removed v ccq and v ssq . requirements for synchronous (burst) read operation, continuous burst first paragraph, bold text, second sentence: the highest address changed to 000000h. reset#: hardware reset input fourth paragraph: t ready changed to tr eadyw . autoselect command sequence added table 11 title, autoselect device id. wp# boot sector protection, low v cc write inhibit, table immediately preceding program comma nd sequence section modified read data for de vice id, word 1, device id, word 2 for s29ns064j only, device id, word 3. table 14, command definitions added notes 10 and 12; changed ba = address of the bank from a22-a20 to a22-a21 for s29ns128j, a21-a19 to a21-a20 for s29ns064j. ac characteristics cmos compatible added i ccw , typ and max values for i ppw and i ccw ; added i cce , typ and max values for i ppe and i cce . ac characteristics, fi gure 15, 16, 18, and 19 changed avd to avd#. revision a2 (august 19, 2003) requirements for synchronou s (burst) read operation modified bold text to indicate ?highest address to 00000h?. revision a3 (september 10, 2003) dc characteristics, cmos compatible changed i cc3 and i cc4 max values. revision a4 (november 13, 2003) global converted to spansion format. revision a5 (february 5, 2004) ordering information added 0l clock rate/asynchronous speed. updated valid combinations to reflect addition. appendix c and d added c and removed d.
march 22, 2006 S29NS-J_00_a10 S29NS-J 79 data sheet revision a6 (april 7, 2004) ordering information removed pb-free compliant options from 32 mega bit and 16 megabit combinations for both 66 mhz and 54 mhz. global corrected figure references. ac characteristics modified the t ready timing in figure 14 in hardware reset (reset#). erase and programm ing performance added density and typical values to a ccelerated chip erase time parameter. data retention remove section. revision a7 (august 4, 2004) global change changed all instances of ?fasl? to ?spansion?. added colophon text. sector erase command sequence replaced ?50 s? with ?t sea (sector erase accept) '. accelerated sector erase groups, s29ns032j replaced ?sa0?sa7? with ?sa0?sa3?. replaced ? sa8?sa15? with ?sa4?sa7?. replaced ? sa16?sa23? with ?sa8?sa11?. replaced ?sa24?sa31? with ?sa56?sa59?. deleted ?sa40?sa47?. deleted ?sa48?sa55?. deleted ?sa48?sa55?. replaced ? sa56?sa62? with ?sa60?sa62?. accelerated sector erase groups, s29ns016j replaced ? sa0?sa7? with ?sa0?sa1?. replaced ? sa8?sa15? with replaced ?sa16?sa23? with replaced ?sa24?sa30? with added the following: sa8-sa9; sa10-sa11; sa12-sa13; sa14-sa15; sa16-sa17; sa18-sa19; sa20-sa21; sa22-sa23; sa24-sa25; sa26-sa27; sa28-sa29; sa30 erase suspend/erase resume commands replaced ?50 s? with ?t sea ?. replaced ?35 s? with ?t esl (erase suspend latency)?. dq7: data# polling replaced ?1 s? with ?t psp ?. replaced ?100 s? with ?t asp (all sectors protected toggle time)?.
80 S29NS-J S29NS-J_00_a10 march 22, 2006 data sheet dq6: toggle bit i replaced ?100 s? with ?t asp ?. replaced ?1 s? with ?t psp ?. dq3: sector erase timer replaced ?50 s? with ?t sea ?. erase and programm ing performance updated ?accelerated chip erase time? as per the following: distinctive characteristics deleted the following: ?minimum 100,000 erase cycle guarantee per sector?. ?20-year data retention?. ?reliable operation for the life of the system?. erase and programm ing performance in note 2 changed ?100,000? to ?1,000,000?. 8-, 16-, and 32-word linear burst address wrap around updated drawing. unlock bypass command sequence removed ?the host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. the erase command sequences are four cycles in length instead of six cycles.? command definitions removed the unlock bypass ?secto r erase? and ?chip erase? rows. table 18, ?command definitions? removed unlock bypass sector erase section. removed chip erase section. wp# boot sector protection updated 2nd paragraph as follows: ?if using the unlock bypass feature: on the 2nd program cy - cle, after the unlock bypass command is written, the wp# signal must be asserted on the 2nd cycle.? global replaced all ?amd? references with ? contact your local spansion sales office?. chip erase command sequence removed ?the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles in length instead of six cycles. sector erase command sequence replaced ?50 s? with ?t sea?. original updated 128mb 45 50 64mb 30 25 32mb tbd 12.5 16mb tbd 6.25
march 22, 2006 S29NS-J_00_a10 S29NS-J 81 data sheet removed the following ?the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles in length instead of six cycles.? erase/program operations removed the following rows from table: revision a8 (september 14, 2004) ordering information added packing types 0 and 2. valid combinations added packing type information. revision a9 (november 11, 2005) added lf35 package ordering option revision a10 (march 22, 2006) global changed v pp to acc. ac characteristics asynchronous read table: updated the values of t aavdh for both speed bins. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuclear reaction control in nucle ar facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch co ntrol in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be lia ble to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures in to your facility and equipment such as redu ndancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2005-2006 spansion llc. all righ ts reserved. spansion, the spansion logo, mirrorbit, combinations thereof are tradem arks of spansion llc. other company and product names used in this publication are for identification purposes only and may be trademarks of their re spective companies. t whwh1 t whwh1 programming operation (note 2) typ 9 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (notes 2, 3) typ 0.4 sec

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